Forming via holes in a multilevel substrate in a single step
US5227013A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 1991 |
| Grant date | Jul 13, 1993 |
| Priority date | — |
| Expiry date | Jul 25, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for forming via holes in a multilayer structure in a single step. The invention includes disposing over a base a first layer comprising first metal lines beneath a first dielectric, disposing over the first layer a second layer comprising second metal lines beneath a second dielectric such that a portion of each first metal line is not beneath any second metal line, and forming via holes which extend through the second dielectric to the second metal lines and through the second dielectric and the first dielectric to the portions of the first metal lines. Thereafter conductive metal can be deposited in the via holes. The method is particularly well suited for fabricating copper/polymer substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.