Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology
US5229331A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1992 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Feb 14, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2209/0226
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.