High density data storage using stacked wafers
US5229647A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1992 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Sep 21, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A solid-state memory unit is constructed using stacked wafers containing a large number of memory units in each wafer. Vertical connections between wafers are created using bumps at the contact points and metal in through-holes aligned with the bumps. The bumps on one wafer make contact with metal pads on a mating wafer. Mechanical bonding between the bumps and mating metal pads on another wafer is preferably avoided so that fractures due to thermal expansion differentials will be prevented. Serial addressing and data access is employed for the memory units to minimize the number of connections needed. Also, the metal pads, through-holes and bumps are formed at corners of the die and thus shared with adjacent units whenever possible, further reducing the number of vertical connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.