DRAM compressed data test mode with expected data
US5231605A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 1991 |
| Grant date | Jul 27, 1993 |
| Priority date | — |
| Expiry date | Jan 31, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A unique method of testing an integrated circuit DRAM for incorrect stored data is disclosed. A JEDEC test mode entry is initiated by normal means, i.e., Write Enable (WE*) and Column Address Select (CAS*) before Row Address Select (RAS*) with specific address data to select a specific test. Data bits are then loaded in the DRAM cells and column data bits compared. The subarray bits are also compared with bits in an expected data register which has been loaded at the beginning of the read cycle. If column bits match and subarray bits match the expected data register, ones are indicated on the data (out) bus; otherwise, a zero appears in case of a data error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.