Maintaining data coherency between a central cache, an I/O cache and a memory
US5247648A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1992 |
| Grant date | Sep 21, 1993 |
| Priority date | — |
| Expiry date | Apr 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/303
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O write back cache memory and a data coherency method is provided to a computer system having a cache and a main memory. The data coherency method includes partitioning the main memory into memory segments, dynamically assigning and reassigning the ownership of the memory segments either to the cache memory or the I/O write back cache memory. The ownership of the memory segments controls the accessibility and cacheability of the memory segments for read and write cycles performed by the CPU and I/O devices. During reassignment, various data management actions are taken to ensure data coherency. As a result, the I/O devices can perform read and write cycles addressed against the cache and main memory in a manner that increases system performance with minimal increase in hardware and complexity cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.