Transistor useful for further vertical integration and method of formation
US5252849A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1992 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | Mar 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.