Cache memory expansion and transparent interconnection
US5253358A · kind A · utility
14Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 1992 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | May 7, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0886
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.