Methods of patterning and manufacturing semiconductor devices
US5256587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1992 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | Jul 10, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled. Where the present invention is applied to capacitors of semiconductor memory elements, the capacitor node surface area can be increased, depending on the etched back depth of a polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.