Low power memory module using restricted RAM activation
US5257233A · kind A · utility
91Cited by
3References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1990 |
| Grant date | Oct 26, 1993 |
| Priority date | — |
| Expiry date | Oct 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module for an electronic device is disclosed which provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.