Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
US5258318A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1992 |
| Grant date | Nov 2, 1993 |
| Priority date | — |
| Expiry date | May 15, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/959
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1,000 .ANG. and bipolar devices formed in a thick epitaxial layer of 1 .mu.m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide-bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1,000 .ANG. over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 .mu.m in the bipolar regions and a 1,000 .ANG. thick layer of epitaxial silicon in the CMOS regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.