Multilayer ceramic substrate with graded vias
US5260519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1992 |
| Grant date | Nov 9, 1993 |
| Priority date | — |
| Expiry date | Sep 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/096
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a multilayer ceramic substrate for electronic applications including: PA0 (a) at least one internal layer having vias filled with a metallic material; PA0 (b) at least one sealing layer having vias filled with a composite material that is a mixture of ceramic and metallic materials; and PA0 (c) at least one transition layer located between the internal and sealing layers having vias filled with a composite material that is a mixture of ceramic and metallic materials but having less ceramic and more metallic material than the sealing layer vias and less metallic material than the internal layer vias. Also disclosed is a method of forming the multilayer ceramic substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.