Semiconductor floating gate device having improved channel-floating gate interaction
US5260593A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1991 |
| Grant date | Nov 9, 1993 |
| Priority date | — |
| Expiry date | Dec 10, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an E.sup.2 PROM design comprising a channel region and a floating gate comprising P-type polycrystalline silicon. The work function difference between P-type material effectively increases the threshold voltage of the transistor. This alleviates the need for a boron V.sub.T adjust implant. Implants of material such as boron to set the threshold voltage are known to correlate with problems such as implant ionization and junction (avalanche) breakdown. These two undesired effects can be decreased or eliminated in devices comprising the invention. An optional phosphorous implant into the substrate would allow the lowering of V.sub.T to a desired level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.