Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices
US5263142A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1992 |
| Grant date | Nov 16, 1993 |
| Priority date | — |
| Expiry date | Dec 28, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O cache is provided to a computer system comprising a main memory and a number of DVMA/DMA I/O devices for caching I/O data between the main memory and the DVMA/DMA I/O devices. The I/O cache selectively caches the I/O data in accordance to the device class types of the DVMA/DMA devices. The I/O cache comprises an I/O cache data array, an I/O cache address tag array, an I/O cache mapper, and I/O cache control logic. The I/O cache data array comprises a number I/O cache lines, each having a number of I/O cache blocks, for storing I/O data between the main memory and the DVMA/DMA devices. The I/O cache tag comprises a number of corresponding I/O cache address tag entries, each having a number of I/O cache address tags and associated control information, for storing address and control information for the I/O data stored in the I/O cache lines. The I/O cache mapper maps the dynamically or statically allocated I/O buffers in main memory of each DVMA/DMA device having a cacheable device class type to a set of dynamically or statically assigned unique I/O cache buffers in the I/O cache data array, thereby ensuring that no two DVMA/DMA devices with cacheable I/O data will share the s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.