Read only memory manufacturing method
US5264386A · kind A · utility
10Cited by
5References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 8, 1992 |
| Grant date | Nov 23, 1993 |
| Priority date | — |
| Expiry date | Sep 8, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
A method for making a Read Only Memory having spaced source and drain regions in a substrate and a plurality of closely spaced gate electrodes on the surface, spanning the distance between the source and drain. The method features the fabrication of a double density polysilicon word line structure for a given integrated circuit chip area. The method also features the formation of a first and a second code ion implant which uses self-alignment techniques, rather than using lithography techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.