Etching processes for avoiding edge stress in semiconductor chip solder bumps
US5268072A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1992 |
| Grant date | Dec 7, 1993 |
| Priority date | — |
| Expiry date | Aug 31, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Etching processes are disclosed for producing a graded or stepped edge profile in a contact pad formed between a chip passivating layer and a solder bump. The stepped edge profile reduces edge stress that tends to cause cracking in the underlying passivating layer. The pad comprises a bottom layer of chromium, a top layer of copper and an intermediate layer of phased chromium-copper. An intermetallic layer of CuSn forms if and when the solder is reflowed, in accordance with certain disclosed variations of the process. In all the variations, the solder is used as an etching mask in combination with several different etching techniques including electroetching, wet etching, anisotropic dry etching and ion beam etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.