Birendra Agarwala
21Patents
14h-index
58Co-inventors
84Inventor score
Filing activity: Sep 5, 1989 → Nov 18, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6734090B2 | Method of making an edge seal for a semiconductor device | Electricity | 559 | Expired |
| US7397260B2 | Structure and method for monitoring stress-induced degradation of conductive interconnects | Electricity | 167 | Expired |
| US5130779A | Solder mass having conductive encapsulating arrangement | Electricity | 132 | Expired |
| US5376584A | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress | Electricity | 109 | Expired |
| US5251806A | Method of forming dual height solder interconnections | Electricity | 106 | Expired |
| US6033939A | Method for providing electrically fusible links in copper interconnection | Electricity | 83 | Expired |
| US5268072A | Etching processes for avoiding edge stress in semiconductor chip solder bumps | Electricity | 74 | Expired |
| US6111321A | Ball limiting metalization process for interconnection | Electricity | 58 | Expired |
| US4970570A | Use of tapered head pin design to improve the stress distribution in the braze joint | Electricity | 27 | Expired |
| US4985310A | Multilayered metallurgical structure for an electronic component | Emerging Cross-Sectional Technologies | 23 | Expired |
| US7224063B2 | Dual-damascene metallization interconnection | Electricity | 22 | Expired |
| US6972209B2 | Stacked via-stud with improved reliability in copper metallurgy | Emerging Cross-Sectional Technologies | 18 | Expired |
| US7279411B2 | Process for forming a redundant structure | Electricity | 17 | Expired |
| US7163883B2 | Edge seal for a semiconductor device | Electricity | 16 | Expired |
| US6271599A | Wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrate | Electricity | 10 | Expired |
| US6825561B1 | Structure and method for eliminating time dependent dielectric breakdown failure of low-k material | Electricity | 6 | Expired |
| US7138714B2 | Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines | Electricity | 6 | Expired |
| US7470613B2 | Dual damascene multi-level metallization | Electricity | 5 | Active |
| US8466056B2 | Method of forming metal interconnect structures in ultra low-k dielectrics | Electricity | 3 | Active |
| US7639032B2 | Structure for monitoring stress-induced degradation of conductive interconnects | Electricity | 2 | Active |
| US7692439B2 | Structure for modeling stress-induced degradation of conductive interconnects | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.