Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
US5270241A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1992 |
| Grant date | Dec 14, 1993 |
| Priority date | — |
| Expiry date | Nov 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.