Multilayer interconnect system for an area array interconnection using solid state diffusion
US5276955A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1992 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Apr 14, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49128
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer. When the conductive pad layers of two or more subsections are aligned and stacked together, the interconnect pads can be mechanically and electrically joined together using solid state diffusion to join the donor metal layer and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.