Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric
US5284801A · kind A · utility
18Cited by
11References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1992 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Jul 22, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits include a silicon substrate having multiple conductive metallization lines placed thereon and vertically spaced apart from each other by polyimide insulating layers wherein a moisture resistant barrier layer is completely interposed between the polyimide layers and each metallization line. The moisture resistant barrier retards corrosion of the metallization lines by reaction products formed by the release of water from the polyimide layer by reducing the amount of water which can penetrate to the metallization lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.