Floating gate memory array device having improved immunity to write disturbance
US5289411A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1992 |
| Grant date | Feb 22, 1994 |
| Priority date | — |
| Expiry date | Mar 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable and erasable floating gate memory array device is disclosed. The array has a plurality of column address lines, a plurality of row address lines, and a plurality of common source lines. Each of the memory cells has one terminal connected to one of the column address lines, another one connected to one of the row address lines, and a third connected to one of the common source lines. By appropriate selection circuit, a high voltage source can be connected to either the row address line to effect erasure of charges on the floating gate of the memory cells connected to the selected row address line or to the common source line to selectively program the memory cells connected to the associated common source line. In this manner, write disturbance can be limited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.