Transistor and a capacitor used for forming a vertically stacked dynamic random access memory cell
US5291438A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1993 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Jul 12, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A transistor and a capacitor is used to provide, in one form, a dynamic random access memory (DRAM) cell (10). The capacitor of cell (10) lies within a substrate (12). The capacitor has a first capacitor electrode (16) and a second capacitor electrode (20). A dielectric layer (18) is formed as an inter-electrode capacitor dielectric. A first transistor current electrode (36) is formed overlying and electrically connected to the first capacitor electrode (16). A channel region (38) is formed overlying the first transistor current electrode (36). A second transistor current electrode (40) is formed overlying the channel region (38). A conductive layer (30) is formed laterally adjacent the channel region (38) and isolated from the substrate (12) by dielectric layers (22 and 28). A conductive layer (30) functions as a gate electrode for the transistor and a sidewall dielectric (34) functions as a gate dielectric. The combination of a cylindrical dual-sidewall surface area capacitor for a large capacitance, along with a vertical transistor physically overlying the capacitor, forms a very dense and efficient DRAM structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.