Array block level redundancy with steering logic
US5295101A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1992 |
| Grant date | Mar 15, 1994 |
| Priority date | — |
| Expiry date | Jan 31, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The described embodiments of the present invention provide a circuit and method for a two level redundancy scheme for a semiconductor memory device. The memory device has one or more data blocks (12) with each data block (12) having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks (14) with each sub-block having a plurality of the memory cells. The first level redundancy scheme includes a few redundant elements for each sub-block for the replacement of defective elements, as is common in many modern semiconductor devices. The second level redundancy scheme includes at least one redundant sub-block of memory cells as part of the main memory for a fully functional memory device or, as an extra level of redundancy for at least one sub-block of memory cells containing defects which are not repairable using the redundant elements. When activated for redundancy, the second level redundancy scheme replaces at least one defective sub-block of memory devices with a like number of redundant sub-blocks of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.