Semiconductor device having a semiconductor substrate with reduced step between memory cells
US5300814A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1992 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Jul 17, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/92
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.