Method for shaping features of a semiconductor structure using chemical mechanical planarization (CMP)
US5302233A · kind A · utility
384Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1993 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Mar 19, 2013 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24B37/04
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
In semiconductor manufacture a method of shaping the features of a semiconductor structure using chemical mechanical planarization (CMP) is provided. During CMP, a relatively soft polishing pad is utilized to conform to and contour a topography of the semiconductor structure. Another layer of a material such as a dielectric (e.g. TEOS based silicon dioxide) can then be deposited over the contoured topography without the inclusion of voids. The method of the invention is particularly suited to the formation of void free dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.