Method of formation of transistor and logic gates
US5308778A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1993 |
| Grant date | May 3, 1994 |
| Priority date | — |
| Expiry date | Jan 11, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with multiple inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.