Semiconductor memory device and method of formation
US5308782A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1992 |
| Grant date | May 3, 1994 |
| Priority date | — |
| Expiry date | Oct 26, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.