IC chip package having chip attached to and wire bonded within an overlying substrate
US5313096A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 1992 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Jul 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC chip package includes a chip having an upper active surface thereof bonded to the lower surface of a substrate. A plurality of terminals on the active surface are wire bonded within the outer periphery of the chip by bonding wires extending through a plurality of apertures in a lower layer of the substrate to bonding pads on an upper surface of the lower substrate layer. Metallized strips couple the bonding pads to conductive pads at the outer edges of the lower substrate layer. The substrate includes an upper layer having apertures therein. After wire bonding, the apertures in the upper and lower substrate layers are filled with epoxy which is cured and then ground flush with the upper surface of the upper substrate layer. The chip is then lapped to a desired thickness, following which the chip package is electrically tested at various temperatures. The chip package is programmed by wire bonding a chip enable trace to one of a plurality of optional bonding pads of a bonding option array on the lower substrate layer, following which an aperture within the upper substrate layer which provides access to the bonding option array is filled with epoxy which is then cured and groun…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.