Apparatus and method for preventing I/O bandwidth limitations in fast fourier transform processors
US5313413A · kind A · utility
56Cited by
7References
12Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 8, 1993 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Mar 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.