Semiconductor device having structures to reduce stress notching effects in conductive lines and method for making the same
US5317185A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1992 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Feb 18, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has structures to reduced stress notching effects in conductive lines. In one form, the semiconductor device includes a semiconductor die which has a plurality of active conductive lines thereon. The plurality of conductive lines collectively has a first and a second outside edge. In close proximity to each of the first and the second outside edges is a stress reducing line. Each of the stress reducing lines is a non-active structure (in other words does not transmit signals) and functions to reduce stress concentrations on the plurality of active conductive lines which are imposed by overlying insulating and passivation layers. As a result of weakened stress concentrations, the amount of stress notching in the active conductive lines is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.