Dynamic content addressable memory device and a method of operating thereof
US5319589A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1992 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Oct 27, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.