High performance integrated circuit chip package

US5325265A · kind A · utility

Assignees

• MCNC · US
• IBM Corporation · US
• Nortel Networks Limited · CA

Inventors

• Iwona Turlik · Raleigh, US
• Arnold Reisman · Raleigh, US
• Deepak Nayak · Kanchinakote, IN
• Lih-Tyng Hwang · Durham, US
• Giora Dishon · Jerusalem, IL
• Scott Jacobs · Randolph, US
• Robert Francis Darveaux · Newport Beach, US
• Neil M. Poley · Kingston, US

Key dates

• Filing date: Jan 7, 1992
• Grant date: Jun 28, 1994
• Expiry date: Jan 7, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/351
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.