Deepak Nayak
59Patents
13h-index
58Co-inventors
87Inventor score
Filing activity: Feb 27, 1990 → Feb 27, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5617991A | Method for electrically conductive metal-to-metal bonding | Electricity | 258 | Expired |
| US5325265A | High performance integrated circuit chip package | Electricity | 158 | Expired |
| US6194259A | Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants | Electricity | 124 | Expired |
| US6506640B1 | Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through | Electricity | 121 | Expired |
| US10339470B1 | Techniques for generating machine learning training data | Physics | 70 | Active |
| US7214629B1 | Strain-silicon CMOS with dual-stressed film | Emerging Cross-Sectional Technologies | 53 | Expired |
| US5824586A | Method of manufacturing a raised source/drain MOSFET | Emerging Cross-Sectional Technologies | 45 | Expired |
| US7429775B1 | Method of fabricating strain-silicon CMOS | Electricity | 34 | Expired |
| US7851313B1 | Semiconductor device and process for improved etch control of strained silicon alloy trenches | Electricity | 24 | Active |
| US9711511B1 | Vertical channel transistor-based semiconductor memory structure | Electricity | 22 | Active |
| US8120075B1 | Semiconductor device with improved trenches | Electricity | 13 | Active |
| US7670923B1 | Method of fabricating strain-silicon CMOS | Electricity | 13 | Active |
| US5817536A | Method to optimize p-channel CMOS ICs using Q.sub.bd as a monitor of boron penetration | Electricity | 13 | Expired |
| US9748335B1 | Method, apparatus and system for improved nanowire/nanosheet spacers | Electricity | 12 | Active |
| US6372590B1 | Method for making transistor having reduced series resistance | Electricity | 12 | Expired |
| US5920104A | Reducing reverse short-channel effect with light dose of P with high dose of as in n-channel LDD | Electricity | 11 | Expired |
| US7423283B1 | Strain-silicon CMOS using etch-stop layer and method of manufacture | Electricity | 9 | Expired |
| US5757204A | "Method and circuit for detecting boron (""B"") in a semiconductor device using threshold voltage (""V"") fluence test" | Physics | 9 | Expired |
| US9941329B2 | Light emitting diodes (LEDs) with integrated CMOS circuits | Electricity | 6 | Active |
| US10388691B2 | Light emitting diodes (LEDs) with stacked multi-color pixels for displays | Electricity | 6 | Active |
| US6051460A | Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon | Emerging Cross-Sectional Technologies | 5 | Expired |
| US7875543B1 | Strain-silicon CMOS using etch-stop layer and method of manufacture | Electricity | 5 | Active |
| US10726060B1 | Classification accuracy estimation | Physics | 4 | Active |
| US10037981B2 | Integrated display system with multi-color light emitting diodes (LEDs) | Electricity | 4 | Active |
| US10249710B2 | Methods, apparatus, and system for improved nanowire/nanosheet spacers | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.