Three dimensional assembly of integrated circuit chips

US5327327A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Dean L. Frew · McKinney, US
• Mark A. Kressley · Richardson, US
• Arthur M. Wilson · Dallas, US
• Juanita G. Miller · Richardson, US
• Philip Hecker · Garland, US
• James Drumm · Dallas, US
• Randall E. Johnson · White Lake, US
• Rick Elder · Houston, US

Key dates

• Filing date: Oct 30, 1992
• Grant date: Jul 5, 1994
• Expiry date: Oct 30, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.