Method of making 0.6 micrometer word line pitch ROM cell by 0.6 micrometer technology
US5330924A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1993 |
| Grant date | Jul 19, 1994 |
| Priority date | — |
| Expiry date | Nov 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/383
Abstract
A cost-effective and manufacturable method for producing ROM integrated circuits with closely-spaced self-aligned conductive lines, on the order of 0.3 micrometers apart, is described. Parallel, conductive semiconductor device structures are formed in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A first conductive polysilicon layer is formed over the insulating layer. The first conductive polysilicon layer is patterned to form first polysilicon conductor lines which are parallel to each other, and orthogonal to the parallel, conductive semiconductor device structures. A first silicon oxide layer is formed on and between the first polysilicon conductor lines. The first silicon oxide layer is anisotropically etched to produce sidewall structures on the first polysilicon conductor lines. A second silicon oxide layer is formed on and between the first polysilicon conductor lines. A second conductive polysilicon layer is formed over the first polysilicon conductor lines and in openings between the first polysilicon conductor lines. The second conductive polysilicon layer is etched back to form second polysilicon conductor lines, parallel to,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.