Semiconductor packages with centrally located electrode pads
US5334873A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 1992 |
| Grant date | Aug 2, 1994 |
| Priority date | — |
| Expiry date | Apr 22, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method for manufacturing such a package in which a desired thickness of the package is accomplished. The package includes a semiconductor chip provided with a plurality of solders which are formed on pads of the chip, respectively, and a plurality of inner leads of a lead frame which are electrically connected to the solders by soldering. The method comprises the steps of coating polyimide layers on a surface of semiconductor chip, forming solders on pads of the chip, soldering inner leads of a lead frame to the solders in order to electrically connect the chip to the inner leads, molding an encapsulation epoxy resin coating in order to cover a predetermined area including the semiconductor chip and the inner leads, and trimming and forming the package having been processed in above steps. The package of this invention provides advantage in that the inner leads are connected to the solders of the chip, thereby accomplishing a desired thickness of the package, reducing manufacturing cost and simplifying the manufacturing process of the package due to removing wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.