Self-aligned contacts with gate overlapped lightly doped drain (goldd) structure
US5340761A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1991 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Oct 31, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for producing a transistor with an overlapping gate region, a gate region is placed on a substrate between two source/drain regions. Spacers are placed around the gate region. The spacers are formed of dielectric material. A thin layer of polysilicon is deposited over the two source/drain regions and over electrically insulating regions adjacent to the two source/drain regions. Portions of the thin layer of polysilicon are oxidized to electrically isolate the two source/drain regions. A metal-silicide layer is formed on the portions of the thin layer of polysilicon which are not oxidized. The metal-silicide layer is connected to a metal layer. The electrical contact of the metal-silicide layer and the metal layer is over an electrically insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.