Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
US5341328A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1992 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Jun 15, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a solid state, directly overwritable, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, single cell memory element having reduced switching current requirements and increased write/erase cycle life. The structurally modified memory element includes an electrical contact formed of amorphous silicon, either alone or in combination with a layer of amorphous carbon layer. The memory element exhibits orders of magnitude higher switching speeds at remarkably reduced switching energy levels. The novel memory elements of the instant invention are further characterized, inter alia, by at least two stable and non-volatile detectable configurations of local atomic and/or electronic order, which configurations can be selectively and repeatably accessed by electrical input signals of designated energies. The reduced switching current requirements and an increased write/erase cycle life are achieved by structurally modifying the electrical contact with the aforementioned layer of amorphous silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.