Method for forming laterally graded deposit-type emitter for bipolar transistor
US5342794A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1993 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Jun 7, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/011
Abstract
The present invention provides a BiCMOS integrated circuit with bipolar, NMOS and PMOS transistors. In a bipolar transistor, an emitter buffer is provided to minimize a hot carrier effect. The emitter buffer is implanted using the same mask used for a base link. However, the n-type dopant is implant using a large angle, while the p-type dopant is implanted using a normal implant. A "base" oxide is grown over the implant region. This oxide ultimate isolates the emitter buffer from the polysilicon emitter contact section. Local interconnects are formed using a "dual-gate" technique, in which a tungsten silicide cap layer is formed over polysilicon to short pn junctions in the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.