Semiconductor integrated circuit device including memory cells having a structure effective in suppression of leak current
US5349218A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 29, 1992 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Apr 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
Abstract
A semiconductor integrated circuit device has a semiconductor memory cell array including word lines, data lines and a plurality of memory cells provided at cross points of the word and data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions formed in a main surface of a semiconductor substrate, a first insulating film formed on the main surface between the first and second doped regions and a control electrode layer formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line, while the control electrode is connected with a word line. The information storage capacitor includes a second insulating film formed on the wall of one trench formed on the main surface of the substrate, an electrode layer formed on the second insulating film and serving as a first electrode of the capacitor, a dielectric film formed on the electrode layer and a conducting material provided to fill a space defined by the dielectric film in the trench and serving as a second electrode of the cap…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.