Method for optimally placing components of a VLSI circuit
US5349536A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1991 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Aug 20, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for placement of components for a VLSI circuit, an initial number of current placements are selected. A greedy optimization is partially performed on each of the current placements. Then, a subset of the current placements which have been partially optimized is selected to be the new current placements. This selection is based on a global cost metric for the current placements. The global cost metric is, for example, based on the total length of all connection line networks for the circuit. The partial optimization and selection are repeated until there is only one current placement. Then, an optimization is performed on the remaining placement to obtain an optimized placement. The optimization is, for example, a completion of the partially performed greedy optimization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.