Sector-based redundancy architecture
US5349558A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1993 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Aug 26, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors. Addressable storage circuitry (314a,314b) is used for storing sector-based redundancy column addresses, each defining a column address containing the defective column of memory cells in the plurality of sectors in association with one of the different redundant column segments to be used in repairing the defective column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.