Flash eeprom array with improved high endurance
US5359558A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1993 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Aug 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance. Sensing circuitry (20) is used to detect column leakage current indicative of an over-erased bit during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell. A data input buffer circuit (26) is used to compare the logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal. A pulse counter (30) is coupled to the data input buffer circuit for counting a plurality of programming pulses applied thereto. The data input buffer circuit selectively connects only certain ones of the columns of bit lines to the pulse counter in which the bit match signal is at a high logic level so as to program back over-erased memory cells connected to only the certain ones of the columns of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.