Wafer level integration and testing

US5366906A · kind A · utility

Assignee

• Lockheed Martin Corporation · US

Inventors

• Robert J. Wojnarowski · Zion, US
• Constantine A. Neugebauer · Schenectady, US
• Wolfgang Daum · Erie, US
• Bernard Gorowitz · Clifton Park, US
• Eric J. Wildi · Lexington, US
• Michael Gdula · Knox, US
• Stanton Earl Weaver · Broadalbin, US
• Anthony A. Immorlica · Manlius, US

Key dates

• Filing date: Oct 16, 1992
• Grant date: Nov 22, 1994
• Expiry date: Oct 16, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/351
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.