Predictive capacitance layout method for integrated circuits
US5367469A · kind A · utility
22Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 13, 1990 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Dec 13, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.