Floating gate memory array with latches having improved immunity to write disturbance, and with storage latches
US5369609A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1992 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | Nov 12, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable and erasable floating gate memory device has two substantially identical sections. Each section has a plurality of column address lines, a plurality of row lines and a plurality of source lines. A first plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same first row line and its source connected to the same first source line. A second plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same second row line, different from the first row line, and its source connected to the same first source line. Associated with each section is a plurality of bit latches, one for each column. Reprogramming data is stored in the bit latches. Data from the bit latches of one section are stored in the first plurality of floating gate memory cells. Data from the bit latches of the other section are stored in the second plurality of floating gate memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.