Method for ESD protection improvement

US5374565A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Chen-Chiu Hsue · Baoshan, TW
• Joe Ko · Hsinchu, TW

Key dates

• Filing date: Oct 22, 1993
• Grant date: Dec 20, 1994
• Expiry date: Oct 22, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

A method of forming an ESD protection device with reduced junction breakdown voltage, simultaneously with an integrated circuit which includes FET devices, and the resultant device structure, are described. A silicon substrate is provided on which there are field oxide regions, gates, and active regions. A first ion implant of a conductivity-imparting dopant is performed in a vertical direction into the active regions of the ESD protection device and the FET devices. A first insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The first insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. A second ion implant of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant is performed into active regions of both the ESD protection device and the FET devices. A second insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The second insulating layer is patterned to form contact openings to the active regions. Finally, a third ion implant of a conductivity-impar…