Method of fabricating high voltage complementary metal oxide semiconductor transistors
US5376568A · kind A · utility
12Cited by
7References
4Claims
0Family size
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Inventor
Key dates
| Filing date | Jan 25, 1994 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Jan 25, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
Abstract
A method for manufacturing CMOS transistors for integrated circuits which have metal gates and heavily doped source and drain electrode regions, thereby improving their resisting capability to a high voltage while reducing cycle time for manufacture. As a result, the performance of the transistors is improved and the cost of manufacture is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.