Method of making an electrically erasable programmable memory device with improved erase and write operation
US5376572A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1994 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | May 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
Abstract
An improved structure and process of fabricating an electrically erasable programmable read only memory device (EEPROM's) wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide is removed forming a depression in the surface. Impurity ions are implanted in the depression forming a highly doped tunneling region. A tunnel oxide layer is formed on the substrate surface fully covering the tunneling region. Next, the floating gate layer is formed on the tunnel oxide layer. The gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the spaced source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact openings are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrically erasable programmable read only memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.