Planarization
US5378318A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1992 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Jun 5, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for improved planarization of surface topographies encountered in semiconductor processing that involve the etch-back of exposed surfaces of an oxide of silicon and a spin-on-glass. The oxide of silicon is chosen to be oxygen-deficient and thus silicon-rich, with a spectroscopically-defined silicon richness coefficient CSR that is greater than 0, and preferably greater than 0.005. A fluorine-containing process gas such as CHF.sub.3 combined with one or more of CF.sub.4, C.sub.2 F.sub.6 and SF.sub.6 can be used in the etch chemistry. Sensitivity of the etch rate to certain parameters, such as the relative surface area of the exposed oxide of silicon and the fraction of fluorine present, is either reduced or eliminated. Improvement and better control of planarization is achieved by the process, resulting in a widening of the etch-back process window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.