Process for producing closely spaced conductive lines for integrated circuits
US5378646A · kind A · utility
27Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1994 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Jul 7, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
Abstract
A process of fabricating a non-volatile read only memory device (ROM) wherein the conductive word lines have desirable very narrow widths and are closely spaced. The invention provides a process for forming word lines with a smaller width and line pitch than is possible with conventional processes. A first set of word lines is formed. Next, a second set of word lines is formed in between the first word lines using oxide spacers to define the second word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.